1. Field of the Invention
The present disclosure generally relates to methods of forming a gate mask for fabricating a structure of gate lines, and, more particularly, to the formation of a gate mask for fabricating a structure of gate lines in hybrid SOI/bulk techniques at advanced technology nodes.
2. Description of the Related Art
In ongoing efforts to comply with the constraints imposed by Moore's Law, fully depleted semiconductor-on-insulator (FDSOI) is currently considered as a very promising basis for next generation technologies in the fabrication of semiconductor devices at technology nodes of 22 nm and beyond. Aside from FDSOI allowing the combination of high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques, the fabrication processes as employed in FDSOI techniques are comparatively simple and actually represent a low risk evolution of conventional planar bulk CMOS techniques when compared to 3-dimensional transistor designs, such as FINFETs.
In general, SOI techniques make use of a special kind of substrate conventionally formed by a silicon layer (sometimes called an active layer) formed on an oxide layer (often referred to as “buried oxide” or “BOX layer”), which is in turn formed on a bulk semiconductor substrate, such as silicon. Generally, there are two types of SOI devices: partially depleted SOI (PDSOI) devices and fully depleted SOI (FDSOI) devices. For example, in an N-type PDSOI MOSFET, a P-type film is sandwiched between a gate oxide (GOX) and the BOX, wherein a thickness of the P-type film is implemented such that the depletion region cannot cover the whole P region. Therefore, to some extent, PDSOI devices behave like bulk MOSFETs.
In FDSOI substrates, the thickness of the semiconductor or active layer is implemented such that the depletion region covers the entire thickness of the semiconductor or active layer. Herein, the BOX layer in FDSOI techniques supports fewer depletion charges than a bulk substrate and an increase in the inversion charges occurs in the fully depleted semiconductor layer, resulting in higher switching speeds for FDSOI devices when compared to PDSOI devices or bulk devices.
In recent attempts to provide a simple way of meeting power/performance targets, back biasing was suggested for FDSOI devices. When adopting the concept of back biasing, a voltage is applied to the bulk substrate just under the BOX layer of target semiconductor devices. In doing so, the electrostatic control of the semiconductor device may be changed and the threshold voltage may be shifted to either obtain more drive current (hence higher performance) at the expense of an increased leakage current (forward back bias, FBB) or to cut leakage current at the expense of reduced performance. While back bias in a planar FDSOI technique is somewhat similar to body bias as implemented in bulk CMOS technologies, it offers a number of key advantages in terms of level and efficiency of the bias that can be applied. For example, back biasing can be utilized in a dynamic way on a block by block basis. It can be used to boost performance during delimited periods of time when maximum peak performance is required from that block. It can also be used to cut leakage during the periods of time when limited performance is not an issue.
The implementation of back bias in the setup of FDSOI techniques involves a local exposure of the bulk substrate by means of a so-called bulk exposed (BULEX) region that is to be contacted. Naturally, the bulk substrate has a height difference relative to an upper surface of the semiconductor or active layer of the adjoining SOI substrate. Accordingly, a step height exists between BULEX regions and the adjacent semiconductor or active layer of the SOI substrate due to the height difference caused by the BOX layer and the semiconductor or active layer of the adjoining SOI substrate. For example, the step height may be in the range from about 20-50 nm in advanced technologies, raising big challenges in front-end-of-line (FEOL) processing of advanced semiconductor devices due to the uneven topography caused by the step height. For example, the step height between the bulk semiconductor material (at the BULEX regions) and the upper surface of the semiconductor or active layer of the adjacent SOI substrate may lead to uncontrollable variations in the critical dimensions, large offsets between critical dimensions of FDSOI and bulk structures, and, particularly, to divots and crevices in lithographical processes where film residues are hard to remove and which can cause shorts and leaks in final circuit structures.
As pointed out above, the height difference between bulk and SOI regions represents a severe issue in the fabrication of hybrid structures employing SOI substrate portions and bulk portions, e.g., in the form of BULEX regions. Conventionally, this issue is addressed by re-growing silicon material on BULEX regions (i.e., the bulk silicon material) within FDSOI techniques for leveling the bulk regions and the SOI regions when forming gate structures. Accordingly, after the formation of BULEX regions, a wafer is planarized by re-growing semiconductor material (e.g., silicon) on the BULEX regions prior to forming gate structures. However, the re-growth of such semiconductor material introduces dislocations at the border between BULEX and SOI regions due to a misalignment of the height level between the re-grown semiconductor material and adjacent SOI regions caused by process tolerances. These dislocations are usually removed when forming shallow trench isolation (STI) structures between BULEX and SOI regions upon recessing the substrate material at the border between the BULEX regions and the SOI regions and filling of the recesses by STI material. However, this approach requires a rather large separation between BULEX and SOI regions because STI structures of a sufficient size to compensate for the dislocations have to be formed.
In view of the above discussion of the related art, it is, therefore, desirable to provide a process flow in hybrid bulk/SOI techniques to address patterning difficulties occurring due to the high topography in gate modules and/or avoiding issues raised in the hybrid techniques as pointed out above.